根据TI在2024/5发布的( SPRUHM8K)，高精度PWM相关的HRCNFG如下图所示：
其中CTLMODE有两种：Duty_Period模式和Phase模式，这表明高精度配置仅支持两种情形，要么实现Phase的高精度配置，要么实现Duty和Period高精度配置。HRPCTL寄存器的HRPE位的作用是确定是否要启用高精度周期。
同时文档的2009页提示：
When high-resolution period mode is enabled, an EPWMxSYNC pulse introduces ±1-2 cycle jitter to the PWM (±1 cycle in up-count mode and ±2 cycle in up-down count mode). For this reason, TBCTL[SYNCOSEL] cannot be set to 1 (CTR = 0 is EPWMxSYNCO source) or 2 (CTR = CMPB is EPWMxSYNCO source). Otherwise, the jitter occurs on every PWM cycle with the synchronization
pulse.
When TBCTL[SYNCOSEL] = 0 (EPWMxSYNCI is EPWMxSYNCO source), a software synchronization pulse can be issued only once during high-resolution period initialization. If a software sync pulse is applied while the PWM is running, the jitter appears on the PWM output at the time of the sync pulse.
这表明高精度周期和多个epwm模块逐周期同步以及多个epwm模块设置动态相移不能同时设置。总的来说高精度周期、高精度占空比、高精度相移有如下限制：
1、高精度模块要么设置为高精度周期+高精度占空比+普通精度相位、高精度占空比+普通精度周期+普通精度相位、高精度相位+普通精度周期+普通精度占空比；
2、高精度死区仅支持up-down计数方式，高精度周期不支持dowm计数方式
上述是我的一点见解，希望能得到诸君的宝贵意见。最后我的需求是配置高精度相移，但是TBPHSHR的描述中显示“Must not be used”。如下所示：
Phase Offset (High Resolution) Register.
TBPHSHR must not be used. Instead TRREM (HRPWM remainder register) must be used to mimic the functionality of TBPHSHR.The lower 8 bits in this register are ignored - writes are ignored and reads return zero
Reset type: SYSRSn
这里建议使用TRREM，但同步事件发生后又会从TBPHSHR中置数到TRREM，因此我究竟需要将相移的高精度部分数据写入TBPHSHR，还是TRREM？
HRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations.This value keeps track of the remainder portion of the HRPWM hardware calculations.
Notes:
1. The lower 8-bits of the TRREM register can be automatically initialized with the TBPHSHR value on a SYNCIN or TBCTL[SWFSYNC] event or DC event (if enabled). The user can also write a value with the CPU.2. Priority of TRREM register updates:
Sync (software or hardware) TBPHSHR copied to TRREM :Highest Priority
HRPWM Hardware (updates TRREM register): Next priority
CPU Write To TRREM Register: Lowest Priority
3. Bit 10 of TRREM register is not used in asymmetrical mode. This bit can be forced to zero.
TRREM will be initialized to 0x0 and 0x100 in Up and Up-down modes respectively.
Asymmetrical Mode:
TRREM[7:0] = TBPHSHR[15:8]
TRREM[10,9,8] = 0,0,0
Symmetrical Mode:
TRREM[7:0] = TBPHSHR[15:8]
TRREM[10,9,8] = 0,0,1
Reset type: SYSRSn
另一方面TRREM是否支持SFO()+AutoConv，也即我是要向TRREM写入(0x100+frac(PHASE)<<8)，还是(0x100+(frac(PHASE)*MEP_step+0.5)<<8)?
