怎么在ISE中进行模块化设计？

您能否向我提供有关模块化设计的更多信息？
在Project Navigator（GUI和Tcl）中，我们支持分区，它允许在下一次迭代中使用上一次运行的实现结果。
该流程将在12.1中得到改进，允许命令行和PlanAhead支持。
Project Navigator将不再支持它。
一个真正的团队设计流程在13.1的路线图上。
凯特



以下为原文

Can you give me some more information about what you mean by Modular Design?   In Project Navigator (GUI and Tcl) we support Partitions which allows implementation results from the previous run to be used in the next iteration.
 
This flow will be improved in 12.1 allowing command line and PlanAhead support.  It will no longer be supported in Project Navigator.
 
A true Team Design flow is on the roadmap for 13.1.
 
Kate

你好！
请允许我在这个主题中添加我的问题，它看起来很合适。
对于我们在大学的项目工作，我们正在寻找将预先放置和预先布线的设计模块（由VHDL源/ NGC核心/等制成）包含在*新项目*中的能力。
带有“ndgbuild -modular initial”/“ngdbuild -modular assemble”等的“模块化设计流程”目前允许的类型（但根据命令行工具文档应该从版本12的ndgbuild中删除）
..为什么？），但跨越多个项目。
所以说在新的ISE项目中使用预先放置/路由的模块就像在编码项目中使用预编译的软件库一样。
此外，问题是是否可以在新项目中实例化此类模块的多个副本，类似RPM，但包括（本地）路由信息。
katem，你能不能给我一些有关Xilinx部分计划内容的信息？
非常感谢提前！
亲切的问候，
Frank Zavelberg



以下为原文

Hello! 
 
Please allow me to add my question to this topic, it seems to fit nicely.
 
For our project work at University, we're looking for the ability to include pre-placed and pre-routed design modules (made from VHDL sources / NGC cores / etc.) into *new projects*. Kind of what the "modular design flow" with "ndgbuild -modular initial" / "ngdbuild -modular assemble" etc. allows at the moment (but which is - according to the command line tools documentation supposed to be removed from ndgbuild with version 12.. why?), but spanning multiple projects.
 
So to speak using a pre-placed/routed module in a new ISE project like one would use a pre-compiled software library in a coding project.
 
In addition, the question is whether it'll be possible to instantiate multiple copies of such a module in a new project, RPM-like, but including (local) routing information.
 
katem, could you maybe give me some information on what is planned regarding this on Xilinx' part? Thanks a lot in advance!
 
 
Kind regards,
Frank Zavelberg
 

模块化设计流程正在被12.1中的分区取代。
它（模块化设计）从未允许预先放置的模块用于不同的设计。
计划是最终完成你想要做的事情......不幸的是，它不会再用于更多版本。
在13.1中，我们将有一个Team Design流程，您可以单独实现模块（但仍然使用顶级设计），然后将它们组合成一个设计。
这确实需要每个人都瞄准相同的设备，包装和速度等级。
在12.1中，您将能够对您尝试做的事情进行非常有限的处理，但是当您针对不同的设计时，它必须具有相同的逻辑层次结构，相同的部件，包和速度，并且实现结果将是
放置在完全相同的物理位置。



以下为原文

The modular design flow is being replaced with Partitions in 12.1.    It (modular design) never did allow a pre-placed module to be used in a different design.    The plan is to do exactly what you want to do eventually...unfortunately it won't be available for several more releases.  In 13.1 we will have a Team Design flow where  you can implement modules seperately (but still with the top level design) and then assemble them all into one design.  This does require everybody to be targeting the same device, package and speed grade.
 
In 12.1, you will be able to do a very limited about of what you are trying to do but when you target a different design, it will have to have the same logical hierarchy, same part, package and speed and the implementation results will be placed in the exact same physical location.

谢谢你的回复，凯特！
（我想这是你的名字？:)）
您是否可以详细说明一部分：12.1中可能出现的“我想要的数量有限”究竟是什么？
鉴于目标部件完全相同，我可以在什么方面保留模块的放置*和*路由并在不同的设计中重复使用？
Project Navigator工具流是否会支持该命令行，还是只通过命令行？
谢谢和亲切的问候，
坦率



以下为原文

Thanks for your reply, Kate! (I suppose that's your first name? :) ) 
 
Could you maybe elaborate on one part still: What exactly is the "limited amount of what I was intending" that will be possible in 12.1? Given that the target part is precisely the same, in what regard can I then preserve placement *and* routing of a module and re-use it in a different design? Will the Project Navigator tool flow support that, or just through command line?
 
Thanks and kind regards,
Frank 
 

你在名字上猜对了:-)
它将通过PlanAhead和命令行支持，但不支持ProjNav。
未记录的流程将在设计中放置和路由moduleA，将其导出然后将moduleA导入另一个具有相同部件，包，速度等级，逻辑层次结构（RTL层次结构甚至顶层设计名称）和相同物理层的设计中
在FPGA中的位置。
这是非常有限的。
凯特



以下为原文

You guessed right on the name :-)
 
It will be supported via PlanAhead and command line but  not ProjNav.
 
An undocumented flow will be to place and route moduleA in Design, export it and then import moduleA into another design that has the same part, package, speed grade, logical hierarchy (RTL hierarchy even the top level design name) and into the same physical location in the FPGA.   It is very limited.
 
Kate