AI01372
19
A0-A18
W
DQ0-DQ7
V
CC
M29F040
G
E
V
SS
8
Figure 1. Logic Diagram
M29F040
4 Mbit (512Kb x8, Uniform Block) Single Supply Flash Memory
NOT FOR NEW DESIGN
M29F040 is replaced by the M29F040B
5V
±
10% SUPP LY VOLTA G E for PROGRAM,
ERASE and READ OPERATIONS
FAST A CCE SS T IME : 70ns
BYTE PROGRAMMING TIME: 10
µ
s typical
ERASE TIME
– Block: 1.0 sec typical
– Chip: 2.5 sec typical
PROGRAM/ERASE CONTROLLER (P/E.C.)
– Program Byte-by-B yte
– Data Polling and Toggle bits Protocol for
P/ E.C. Sta t us
MEMO RY ERASE in BLOC KS
– 8 Uniform Blocks of 64 KBytes each
– Block Protection
– Multiblock Erase
ERASE SUSPEND and RESUME MODES
LOW POWE R CO NSUMP TION
– Read mode: 8mA typical (at 12MHz)
– Stand-by mode: 25
µ
A typical
– Automatic Stand-by mode
100,000 PROGRAM/ERASE CYCLES per
BLOCK
20 YEARS DATA RETENTION
– Defectivity below 1ppm/year
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: E2h
A0-A18 Address Inputs
DQ0-DQ7 Data Input / Outputs
E Chip Enable
G Output Enable
W Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
PLCC32 (K) TSOP32 (N)
8 x 20 mm
November 1999 1/31
This is information on a product still in production but not recommended for new designs.
